1T-RAM is a 0.25 μm logic-based DRAM that easily fails due to high junction leakage current created by the logic process. In the current process, resist protect oxide (RPO) is used where it is desired that silicidation not take place, for example ESD device or non-silicide resistor.
U.S. Pat. No. 6,015,730 to Wang et al. and U.S. Pat. No. 5,863,820 to Huang each describe salicide processes with an resist protect oxide (RPO) protective step.
U.S. Pat. No. 6,048,738 to Hsu et al. describes a process for fabricating a 1T ferroelectric random access memory (FRAM) for a VLSI RAM array.
U.S. Pat. No. 6,091,106 to Park describes an SRAM process forming a transistor structure having a grooved gate.
U.S. Pat. No. 5,918,148 to Sato describes a 1T SRAM process wherein the reduction in product quality and yield due to the partial reduction in restoring level, a lag of timing, can be avoided.
U.S. Pat. No. 5,434,438 to Kuo describes a 1T and one capacitor memory device